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- Hemani, Ahmed, et al.
(författare)
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High-level synthesis of control and memory intensive communication systems
- 1995
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Ingår i: ; , s. 185-191
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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- Horn, Wolfgang, et al.
(författare)
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Hardware synthesis of an ATM multiplexer from SDL to VHDL : a case study
- 1999
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Ingår i: VLSI ’99. Proceedings IEEE Computer Society Workshop On. ; , s. 100-105
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Konferensbidrag (refereegranskat)abstract
- Hardware synthesis of SDL models poses several problems, because SDL uses Communicating Sequential Processes (CSP) paradigm for system specification. It allows dynamic processes and its semantics assume an infinite FIFO buffer at the input of each process for inter-process communication. We had presented previously a methodology and later refined it for efficient hardware synthesis from SDL specification. In this paper we describe the experience of applying this methodology to a large case study. The case study is an ATM Multiplexer which exhibits a complex control flow and uses large tables. It was modelled using multiple processes. Hardware synthesis was carried out using the methodology starting from its SDL model. The results show that the methodology leads to a correct and efficient hardware implementation. In particular, the methodology avoids use of costly FIFO buffers for implementing inter-process communication and allows sharing of hardware resources among various instances of the same process. The final implementation also meets the 155 Mbit/sec data rate performance requirement
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- Svantesson, Bengt, et al.
(författare)
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A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts
- 1996
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: Characterise CMISTs from the synthesis viewpoint; Contend that the synthesis demands of CMISTs can be met within the framework of a general purpose High-level synthesis tool, by making parts of it adaptive to the input, rather than develop a complete tool for a particular type of application; Present an allocation strategy that automatically adapts for CMISTs; Present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; Present the results of applying the synthesis methodology to the OAM as a test case. The results are compared with the result from two commercial High-level synthesis tool; Prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our obtained by designing manually at register-transfer level; The results is also compared with the results from two commercial HLS tools.
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